This paper presents a bi-directional synchronized communication channel (full-duplex) regardless of LVDS interface use. Due to this possible low performance in data transmission, systems using these resources will have to reduce their logic module speed to suit the channel and thereby reduce the incidence of communication error. This is because of all FPGA I/O (Input/Output) pins that are generally subject to physical interference. Data transmission performed without these resources can lead to errors in data transfer when the transmission rate is high, as there is no guarantee that data integrity is maintained. Other factors such as distance between tracks, resistance, and capacitance balance are important and need to be observed by this type of platform manufacturers. However, some platforms available in the market were not designed to accommodate the LVDS FPGA pin resources in their communication lines, thus preventing the LVDS transceiver use and therefore hindering the implementation of communication channels with high performance. This configuration enables busses to achieve transfer rates of about 10 Gbps by using more advanced devices such as the Xilinx Virtex family of FPGAs, Altera Stratix V FPGAs.Ĭurrently, many FPGAs support LVDS interfaces, and by being properly allocated on the platform, they can provide data communication at a high transmission rate by using their transceivers. The use of this feature enables data transmission between devices to be performed more efficiently, allowing a more secure communication when facing electromagnetic interference. This type of signaling allows signal sending at high speed through a differential pair of parallel wire. This type of communication in next-generation FPGAs is usually established through type interfaces low-voltage differential signaling (LVDS).
For these systems to work efficiently using existing resources in FPGAs, an efficient communication must exist between the FPGAs available on the platform. Platforms that involve multiple field-programmable gate arrays (FPGAs) have been the target of several study fields such as prototyping of MPSoCs (multiprocessor system-on-chip), acceleration, and encryption algorithms. The channel has been validated on a commercial platform with success and the synthesis results, as well as the performance results obtained by using it in a real implementation of the RTM algorithm, are also presented. The channel has been implemented in a PROCStarIII platform and rates of 4.76 Gbps were achieved. A mechanism for dynamic and automatic clock phase adjustment used on the bus was also implemented to ensure that the developed modules were compatible with other platforms. An error detection module was also designed to ensure the sending integrity and correct any errors on the bus. This approach promotes a stable communication between these devices without the use of LVDS pins. This paper presents an inter-FPGAs communication channel based on a DDR interface directed to this kind of platform.
Unfortunately, many platforms available in the market do not observe such restrictions, limiting the throughput of the bus.
Another important factor is that the routing that interconnects the LVDS pins on the platform should be precisely developed to avoid instabilities in communication. Such systems require a data bus dedicated to the communication between FPGAs, which could be done through a LVDS type. Nowadays, systems involving multiple FPGAs are used for various scientific applications.
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